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march 2010 doc id 12754 rev 4 1/35 35 l6726a single phase pwm controller feature flexible power supply from 5 v to 12 v power conversion input as low as 1.5 v 1% output voltage accuracy high-current integrated drivers adjustable output voltage 0.8 v internal reference sensorless and programmable ocp across low-side r dson oscillator internally fixed at 270 khz programmable soft-start ls-less start up disable function fb disconnection protection so-8 package applications subsystem power supply (mch, ioch, pci...) memory and termination supply cpu and dsp power supply distributed power supply general dc / dc converters table 1. device summary description l6726a is a single-phase step-down controller with integrated high-current drivers that provides complete control logic, protections and reference voltage to realize in an easy and simple way general dc-dc converters by using a compact so-8 package. device flexibility allows managing conversions with power input v in as low as 1.5 v and device supply voltage ranging from 5 v to 12 v. l6726a provides simple control loop with trans- conductance error amplifier. the integrated 0.8 v reference allows regulating output voltage with 1% accuracy over line and temperature variations. oscillator is internally fixed to 270 khz. l6726a provides programmable over current protection. current information is monitored across the low-side mosfet r dson saving the use of expensive and space-consuming sense resistors. fb disconnection protection prevents excessive and dangerous output voltages in case of floating fb pin. so-8 order codes package packaging l6726a so-8 tube l6726atr so-8 tape and reel www.st.com
contents l6726a 2/35 doc id 12754 rev 4 contents 1 typical application cir cuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 soft start and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 low-side-less start up (lsless) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 enable / disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1.1 overcurrent threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 feedback disconnection protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3 undervoltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.3 soft-start time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.4 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.5 embedding l6726a-based vrs? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
l6726a contents doc id 12754 rev 4 3/35 9 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1 output inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.2 output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.3 input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 20 a demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.1 board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.1.1 power input (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.1.2 power output (vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.1.3 ic additional supply (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.1.4 test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.1.5 demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11 5 a demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.1 board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.1.1 power input (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.1.2 power output (vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.1.3 ic additional supply (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.1.4 test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.1.5 demonstration board efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
typical application circuit and block diagram l6726a 4/35 doc id 12754 rev 4 1 typical application circuit and block diagram 1.1 application circuit figure 1. typical application circuit 1.2 block diagram figure 2. block diagram 1 2 8 boot ugate phase lgate / oc 4 hs ls v in = 1.5v to 19v (1) l c out vout load c hf c bulk c dec gnd 3 r fb comp / dis 7 r f c f c p vcc r os v cc = 5v to 12v 5 6 fb l6726a reference schematic (1) up to 12v with vcc > 5v l6726a r ocset r d c sn r sn c boot r ghs r gls d vcc boot lgate / oc fb ugate comp / dis gnd adaptive anti cross conduction hs ls vcc transconductance error amplifier + - 0.8v oscillator pwm phase control logic & protections v octh disable i ss ocp clock s r q l6726a i ocset
l6726a pins description and connection diagrams doc id 12754 rev 4 5/35 2 pins description and connection diagrams figure 3. pins connection (top view) 2.1 pin descriptions table 2. pins descriptions 1 2 3 4 vcc fb comp / dis phase lgate / oc gnd ugate boot 5 6 7 8 l6726a pin n name function 1boot hs driver supply. connect through a capacitor (100 nf) to the floating node (ls-drain) pin and provide necessary bootstrap diode from vcc. 2 ugate hs driver output. connect to hs mosfet gate. 3gnd all internal references, logic and drivers are connected to this pin. connect to the pcb ground plane. 4 lgate / oc lgate . ls driver output. connect to ls mosfet gate. oc . over current threshold set. during a short period of time following vcc rising over uvlo threshold, a 10 a current is sourced from this pin. connect to gnd with an r ocset resistor greater than 5k to program oc threshold. the resulting voltage at this pin is sampled and held internally as the oc set point. maximum programmable oc threshold is 0.55 v. a voltage greater than 0.75v (max) activates an internal clamp and causes oc threshold to be set at 400 mv. r ocset not connected sets the 400 mv default threshold. 5vcc device and ls driver power supply. operative range from 4.1 v to 13.2 v. filter with at least 1 f mlcc to gnd. 6fb error amplifier inverting input. connect with a resistor r fb to the output regulated voltage. additional resistor r os to gnd may be used to regulate voltages higher than the reference. 7 comp / dis comp. error amplifier output. connect with an r f - c f // c p to gnd to compensate the device control loop in conjunction to the fb pin. during the soft-start phase, a 10 a current is sourced from this pin so the compensation capacitors also act to program the ss time. dis. the device can be disabled by pulling this pin lower than 0.4 v (min). setting free the pin, the device enables again. 8 phase hs driver return path, current-reading and adaptive-dead-time monitor. connect to the ls drain to sense r dson drop to measure the output current. this pin is also used by the adaptive-dead-time control circuitry to monitor when hs mosfet is off.
pins description and connection diagrams l6726a 6/35 doc id 12754 rev 4 2.2 thermal data table 3. thermal data symbol parameter value unit r thja thermal resistance junction to ambient (1) 1. measured with the component mounted on a 2s2p board in free air (6.7 cm x 6.7 cm, 35 m (p) and 17.5 m (s) copper thickness). 85 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range -20 to 150 c
l6726a electrical specifications doc id 12754 rev 4 7/35 3 electrical specifications 3.1 absolute maximum ratings table 4. absolute maximum ratings 3.2 electrical characteristics v cc = 12 v; t a = -20 c to +85 c unless otherwise specified. symbol parameter value unit v cc to gnd -0.3 to 15 v v boot to phase to gnd 15 45 v v ugate to phase to phase; t < 50ns to gnd -0.3 to (v boot - v phase ) + 0.3 -1 v boot + 0.3 v v phase to gnd -8 to 30 v v lgate to gnd to gnd; t < 50ns -0.3 to v cc + 0.3 -2.5 v fb, comp to gnd -0.3 to 3.6 v table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit recommended operating conditions v cc device supply voltage see figure 1 4.1 13.2 v v in conversion input voltage 13.2 v v cc < 7.0 v 19.0 v supply current and power-on i cc vcc supply current ugate and lgate = open 6 ma i boot boot supply current ugate = open; phase to gnd 0.5 ma uvlo vcc turn-on vcc rising 4.1 v hysteresis 0.2 v oscillator f sw main oscillator accuracy t a = 0 c to +70 c 243 270 297 khz 225 270 315 v osc pwm ramp amplitude 1.1 v d max maximum duty cycle 80 %
electrical specifications l6726a 8/35 doc id 12754 rev 4 reference output voltage accuracy v out = 0.8 v, t a = 0 c to 70 c -1 - 1 % v out = 0.8 v -1.5 - 1.5 transconductance error amplifier gm transconductance (1) 5ms i fb input bias current sourced from fb 100 na a 0 open loop gain (1) 70 db f 0 unity gain (1) 4mhz i comp current capability source current 360 a sink current -360 a soft-start and disable i ss soft-start current from comp pin 10 a dis disable threshold comp falling 0.4 0.5 v gate drivers i ugate hs source current boot - phase = 5 v to 12 v 1.5 a r ugate hs sink resistance boot - phase = 5 v to 12 v 1.1 i lgate ls source current vcc = 5 v to 12 v 1.5 a r lgate ls sink resistance vcc = 5 v to 12 v 0.65 over-current protection i ocset ocset current source sourced from lgate pin. see section 7.1.1 10 a v oc_sw oc switch-over threshold v lgate/oc rising 780 mv v octh_fixed fixed oc threshold v phase to gnd -400 mv 1. guaranteed by design, not subject to test. table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
l6726a device description doc id 12754 rev 4 9/35 4 device description l6726a is a single-phase pwm controller with embedded high-current drivers that provides complete control logic and protections to realize in an easy and simple way a general dc- dc step-down converter. designed to drive n-channel mosfets in a synchronous buck topology, with its high level of in tegration this 8-pin device allows reducing cost and size of the power supply solution. l6726a is designed to operate from a 5 v or 12 v supply bus. thanks to the high precision 0.8v internal reference, the output voltage can be precisely regulated to as low as 0.8 v with 1% accuracy over line and temperature variations (between 0 c and +70 c). the switching frequency is internally set to 270 khz. this device provides a simple control loop with externally compensated transconductance error-amplifier and programmable soft start. low-side-less feature allows the device to perform soft-start over pre-charged output avoiding negative spikes at the load side. in order to avoid load damages, l6726a provides programmable threshold over current protection. output current is monitored across low-side mosfet r dson , saving the use of expensive and space-consuming sense resistor. l6726a also features fb disconnection protection, preventing dangerous uncontrolled output voltages in case of floating fb pin.
driver section l6726a 10/35 doc id 12754 rev 4 5 driver section the integrated high-current drivers allow using different types of power mosfet (also multiple mosfets to reduce the equivalent r dson ), maintaining fast switching transition. the driver for high-side mosfet uses boot pin for supply and phase pin for return. the driver for low-side mosfet uses the vcc pin for supply and gnd pin for return. the controller embodies an anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time, maintaining good efficiency while saving the use of schottky diode: to check for high-side mosfet turn off, phase pin is sensed. when the voltage at phase pin drops down, the low-side mosfet gate drive is suddenly applied; to check for low-side mosfet turn off, lgate pin is sensed. when the voltage at lgate has fallen, the high-side mosfet gate drive is suddenly applied. if the current flowing in the in ductor is negative, voltage on phase pin will never drop. to allow the low-side mosfet to turn-on even in this case, a watchdog controller is enabled: if the source of the high-side mosfet doesn't drop, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate. this mechanism allows the system to regulate even if the current is negative. power conversion input is flexible: 5 v, 12 v bus or any bus that allows the conversion (see maximum duty cycle limitation and recommended operating conditions) can be chosen freely.
l6726a driver section doc id 12754 rev 4 11/35 5.1 power dissipation l6726a embeds high current mosfet drivers for both high side and low side mosfets: it is then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. two main terms contribute in the device power dissipation: bias power and drivers power. device bias power (p dc ) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply hs and ls drivers with the same vcc of the device): drivers power is the power needed by the driver to continuously switch on and off the external mosfets; it is a function of the switching frequency, the voltage supply of the driver and total gate charge of the selected mosfets. it can be quantified considering that the total power p sw dissipated to switch the mosfets (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic mosfet resistance and intrinsi c driver resistance. this last term is the important one to be determined to calculate the device power dissipation. the total power dissipated to switch the mosfets results: where v boot - v phase is the voltage across the bootstrap capacitor. external gate resistors helps the device to dissipate the switching power since the same power p sw will be shared between the internal driv er impedance and the external resistor resulting in a general cooling of the device. figure 4. soft start (left) and disable (right) p dc v cc i cc i boot + () ? = p sw f sw q ghs v boot v phase ? () q gls v cc ? + ? [] ? =
soft start and disable l6726a 12/35 doc id 12754 rev 4 6 soft start and disable l6726a implements a soft start to smoothly charge the output filter avoiding high in-rush currents to be required from the input power supply. the device sources a 10 a soft start current from comp, linearly charging the compensation network capacitors. the ramping comp voltage is compared to the oscillator triangular waveform generating pwm pulses of increasing width that charge the output capacitors. when the fb voltage crosses 800 mv, the output voltage is in regulation: soft start phase will end and the transconductance error amplifier output will be enabled closing the control loop. in the event of an over curren t during soft start, the over current logic will override the soft start sequence and will shut down the pwm logic and both the hi gh side and low side gates. this condition is latched, cycle vcc to recover. the device sources soft start current only when vcc power supply is above uvlo threshold and over current threshold setting phase has been completed. 6.1 low-side-less start up (lsless) l6726a performs a special sequence in enabling ls driver to switch: during the soft-start phase, the ls driver results disabled (ls = off) until the hs starts to switch. this avoids the dangerous negative spike on the output voltage that can happen if starting over a pre- charged output and limits the output discharge (amount of output discharge depends on programmed ss time length: the shorter the programmed ss, the more limited the output discharge). if the output voltage is pre-charged to a voltage higher than the final one, the hs would never start to switch. in this case, ls is enabled and discharges the output to the final regulation value. figure 5. lsless startup (left) vs non-lsless startup (right) 6.2 enable / disable the device can be disabled by pushing comp / dis pin under 0.4 v (min). in this condition hs and ls mosfets are turned off, and the 10 a ss current is sourced from comp / dis pin. setting free the pin, the device enables again performing a new ss.
l6726a protections doc id 12754 rev 4 13/35 7 protections 7.1 overcurrent protection the overcurrent feature protects the converter from a shorted output or overload, by sensing the output current information across the low side mosfet drain-source on-resistance, r dson . this method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. the low side r dson current sense is impl emented by comparing t he voltage at the phase node when ls mosfet is turned on with the programmed ocp threshold voltage, internally held. if the monitored voltage drop (gnd to phase) exceeds this threshold, an overcurrent event is detected. if two overcurrent events are detected in two consecutive switching cycles, the protection will be triggered and the device will turn off both ls and hs mosfets in a latched condition. to recover from over current protection triggered, vcc power supply must be cycled. 7.1.1 overcurrent threshold setting l6726a allows to easily program an overcurrent threshold ranging from 50 mv to 550 mv, simply by adding a resistor (r ocset ) between lgate and gnd. during a short time following vcc rising over uvlo threshold, an internal 10a current (i ocset ) is sourced from lgate pin, determining a voltage drop across r ocset . this voltage drop will be sampl ed and internally held by the devi ce as overcurren t threshold. the oc setting procedure overall time length ranges from 5.5 ms to 6.5 ms, proportionally to the threshold being set. connecting a r ocset resistor between lgate and gnd, the programmed threshold will be: r ocset values range from 5 k to 55 k . if the voltage drop across r ocset is too low, the system will be very sensitive to start-up inrush current and noise. this can result in undesired ocp triggering. in this case, consider increasing r ocset value. in case r ocset is not connected, the device switc hes the ocp threshold to a 400 mv default value: an internal safety clamp on lgate is triggered as soon as lgate voltage reaches 700 mv (typ), enabling the 400 mv default threshold and suddenly ending oc setting phase. see figure 6 for oc threshold setting procedure ti mings picture and oscilloscope sample waveforms. 7.2 feedback discon nection protection in order to provide load protection even if fb pin is not connected, a 100 na bias current is always sourced from this pin. if fb pin is not connected, bias current will permanently pull up fb: this forces comp pin low, avoiding output voltage rising to dangerous levels. i octh i ocset r ocset ? r dson ---------------------- --------------------- - =
protections l6726a 14/35 doc id 12754 rev 4 figure 6. oc threshold setting procedure timings (top) and waveforms (bottom) 7.3 undervoltage lock out in order to avoid anomalous behaviors of the device when the supply voltage is too low to support its internal rails, uvlo is provided: the device will start up when vcc reaches uvlo upper threshold and will shutdown when vcc drops below uvlo lower threshold. the 4.1 v maximum uvlo upper threshold allows l6726a to be supplied from 5 v and 12 v busses in or-ing diode configuration. figure 7. ocp trip, default threshold, ls: std38nh02l (left) uvlo turn off (right) vcc enable th comp 700mv lgate pwm ramp bottom edge uvlo th r ocset not connected setting procedure vcc enable th comp 700mv lgate pwm ramp bottom edge uvlo th 5.5ms - 6.5ms r ocset connected setting procedure t delay t delay
l6726a application details doc id 12754 rev 4 15/35 8 application details 8.1 output voltage selection l6726a is capable to precisely regulate an output voltage as low as 0.8 v. in fact, the device comes with a fixed 0.8 v internal reference that guarantees the output regulated voltage to be within 1% tolerance over line and temperature variations between 0 c and 70 c (excluding output resistor divider tolerance, when present). output voltage higher than 0.8 v can be achieved by adding a resistor r os between fb pin and ground. referring to figure 1 , the steady state dc output voltage will be: where v ref is 0.8 v. 8.2 compensation network the control loop shown in figure 8 is a voltage mode control lo op. the error amplifier is a transconductance type with fixed gain (3.3 ms typ.). the fb voltage is regulated to the internal reference, thus the output voltage is fixed accordingly to the output resistor divider (when present). transconductance error amplifier output current generates a voltage across z f , which is compared to oscillator saw-tooth waveform to provide pwm signal to the driver section. pwm signal is then transferred to the switching node with v in amplitude. this waveform is filtered by the output filter. figure 8. pwm control loop the converter transfer function is the small signal transfer function between the voltage at the output node of the ea (comp) and v out . this function has a double pole (complex conjugate) at frequency f lc depending on the l-c out resonance and a zero at f esr v out v ref 1 r fb r os ---------- - + ?? ?? ? = l r c out esr r fb osc v in v osc + + _ _ v out v ref z f output divider pwm comparator ota r f c f c p r os fb comp
application details l6726a 16/35 doc id 12754 rev 4 depending on the output capacitor esr. the dc gain of the modulator is simply the input voltage v in divided by the peak-to-peak oscillator voltage v osc . v out is scaled and transferred to fb node by the output resistor divider. the compensation network closes the loop joining fb and comp node with transfer function ideally equal to -gm z f . compensation goal is to close the control loop assuring high dc regulation accuracy, good dynamic performances and stability. to achiev e this, the overall loop needs high dc gain, high bandwidth and good phase margin. high dc gain is achieved giving an integrator shape to compensation network transfer function. loop bandwidth (f 0db ) can be fixed choosing the right r f ; however, for stability, it should not exceed f sw /2 . to achieve a good phase margin, the control loop gain has to cross 0 db axis with -20 db/decade slope. as an example, figure 9 shows an asymptotic bode plot of a type ii compensation. figure 9. example of type ii compensation. open loop converter singularities: a) b) compensation network singularities frequencies: a) b) gain [db] log (freq) 0db ota open loop gain closed loop gain compensation gain converter open loop gain f lc f esr f z f p 20log (gmr f ) 20log [v in / v osc r os /(r fb +r os )] f 0db f lc 1 2 lc out ? ---------------------------------- = f esr 1 2 c out esr ?? ------------------------------------------- - = f z 1 2 r f c f ?? ------------------------------ = f p 1 2 r f c f c p ? c f c p + -------------------- - ?? ?? ?? -------------------------------------------------- =
l6726a application details doc id 12754 rev 4 17/35 type ii compensation relies on the zero introduced by the output capacitors bank to achieve stability. thus, a needed cond ition to successfully appl y type ii compensation is (usually true when output capacitor is based on electrolytic, aluminium electrolytic or tantalum capacitor). to define compensation network components values, the below suggestions may be followed: a) set the output resistor divider in order to obtain the desired output voltage: usual values of r fb and r os ranges from some hundreds of to some k (consider trade-off between power dissipation on output resistor divider and offset introduced by fb bias current). if the desired output voltage is equal to internal reference, r os has to be nc and fb pin can be directly connected to v out . b) set r f in order to obtain the desired closed loop regulator bandwidth according to the approximated formula: if v out = v ref , just consider (r fb +r os )/r os factor equal to 1. c) place f z below f lc (typically 0.2 f lc ): d) place f p at 0.5 f sw : e) check that compensation network gain is lower than open loop transconductance ea gain. f) estimate phase margin obtained (it should be greater than 45) and repeat, modifying parameters, if necessary. f esr f 0db < r fb r os ----------- v out v ref -------------- 1 ? = r f f 0db f esr ? f lc 2 ------------------------------- v osc v in ------------------ - 1 gm -------- r fb r os + r os ---------------------------- ??? = c f 5 2 r f f lc ?? --------------------------------- = c p c f r f c f f sw 1 ? ??? ---------------------------------------------------- 1 r f f sw ?? ------------------------------- ? =
application details l6726a 18/35 doc id 12754 rev 4 8.3 soft-start time calculation to calculate ss time (t ss ), the following approximated equation can be used (c p < l6726a application details doc id 12754 rev 4 19/35 connect output bulk capacitors (c out ) as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace, also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitors bank. gate traces and phase trace must be sized according to the driver rms current delivered to the power mosfet. the device robustness allows managing applications with the power section far from the controller without losing performances. anyway, when possible, it is recommended to minimize the distance between controller and power section. see figure 11 for drivers current paths. small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. locate bypass capacitor (vcc and bootstrap capacitor) and loop compensation components as close to the device as practical. for over curren t programmability, place r ocset close to the device and avoid leakage current paths on lgate / oc pin, since the internal current source is only 10 a systems that do not use schottky diode in parallel to the low-side mosfet might show big negative spikes on the phase pin. this spike must be limited within the absolute maximum ratings (for example, adding a gate resistor in series to hs mosfet gate, or a phase resistor in series to phase pin), as well as the positive spike, but has an additional consequence: it causes the bootstrap capacitor to be over-charged. this extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the absolute maximum ratings also causing device failures. it is then suggested in this case to limit this extra-charge by adding a small resistor in series to the bootstrap diode (r d in figure 1 ). figure 11. drivers turn -on and turn-off paths r gate r int c gd c gs c ds vcc ls driver ls mosfet gnd lgate r gate r int c gd c gs c ds boot hs driver hs mosfet phase ugate r phase
application details l6726a 20/35 doc id 12754 rev 4 8.5 embedding l6726a-based vrs? when embedding the vr into the application, additional care must be taken since the whole vr is a switching dc/dc regulator and the most common system in which it has to work is a digital system such as mb or similar. in fact, latest mbs have become faster and more powerful: high speed data busses are more and more common and switching-induced noise produced by the vr can affect data integrity if additional layout guidelines are not followed. few easy points must be considered mainly when routing traces in which switching high currents flow (switching high currents cause voltage spikes across the stray inductance of the traces causing noise that can affect the near traces): when reproducing high current path on internal layers, keep all layers the same size in order to avoid ?surrounding? effects that increase noise coupling. keep safe guard distance between high current switching vr traces and data busses, especially if high-speed data busses, to minimize noise coupling. keep safe guard distance or f ilter properly when routing bias traces for i/o sub-systems that must walk near the vr. possible causes of noise can be located in the phase c onnections, mosfets gate drive and input voltage path (from input bulk capa citors and hs drain). also gnd connection must be considered if not insisting on a power ground plane. these connections must be carefully kept far away from noise-sensitive data busses. since the generated noise is mainly due to the switching activity of the vr, noise emissions depend on how fast the current switches. to reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope and thus to increase the switching times: this will cause, as a consequen ce of the higher swit ching time, an increase in switching losses that must be consid ered in the thermal design of the system.
l6726a application information doc id 12754 rev 4 21/35 9 application information 9.1 output inductor inductor value is defined by a compromise between dynamic response, ripple, efficiency, cost and size. usually, inductance is calculat ed to maintain induct or ripple current ( i l ) between 20% and 30% of maximum output current. given the switching frequency (f sw ), the input voltage (v in ), the output voltage (v out ) and the desired ripple current ( i l ), inductance can be calculated as follows: figure 12 shows the ripple current vs. the output voltage for different inductance, with v in = 5 v and v in = 12 v. increasing inductance reduces inductor ripple current (and output voltage ripple accordingly) but, at the same time, increases the converter response time to load transients. higher inductance means that the inductor needs more time to change its current from initial to final value. until the inductor has not finished its charging, the additional output current is supplied by output capacitors. minimizing the response time lead to minimize the output capacitance required. if the compensation network is designed with high bandwidth, during an heavy load transient the device is able to saturate duty cycle (0% or 80%). when this condition is reached, the response time is limited only by the time required to charge the inductor. figure 12. inductor current ripple vs output voltage l v in v out ? f sw i l ? ----------------------------- - v out v in -------------- ? = 0 2 4 6 8 10 12 012345 i n d u c t o r c u r r e n t r i p p l e [ a ] output voltage [v] vin=12v, l=1uh vin=12v, l=2uh vin=5v, l=500nh vin=5v, l=1.5uh
application information l6726a 22/35 doc id 12754 rev 4 9.2 output capacitors output capacitors choice depends on the application constraints in point of output voltage ripple and output voltage deviation during a load transient. during steady-state conditions, the output voltage ripple is influenced by esr and capacitance of the output capacitors as follows: where i l is the inductor current ripple. these contribution are not in phase, so total ripple will be lower than the sum of their moduli. ev en esl and board paras itic inductance can contribute significantly to output ripple. during a load variation, the output capacitors supply to the load the additional current or absorb the current in excess delivered by the inductor until converter reaction is completed. in fact, even if the controller react immediately to the load transient saturating the duty cycle to 80% or 0%, the current slew rate is limited by the inductance. at first approximation, output voltage drop, based on esr and capacitor charge/discharge and considering an ideal load-step, can be estimated as follows: where v l is the voltage applied to the inductor during the transient ( for the load appliance or v out for the load removal). mlcc capacitors typically have low esr to minimize the ripple but also have low capacitance that do not minimize the capaciti ve voltage deviation during load transient. on the contrary, electrolytic capacitors usually ha ve higher capacitance to minimize capacitive voltage deviation during load transient, but also higher esr value resulting in higher ripple voltage and resistive voltage drop. for these reasons, a mix between electrolytic and mlcc capacitor is usually suggested to minimize ri pple as well as reducing voltage deviation in dynamic conditions. 9.3 input capacitors the input capacitor bank is designed mainly to stand input rms current, which depends on output current (i out ) and duty-cycle (d) for the regulation as follows: the equation reaches its maximum value, i out /2, when d = 0.5. losses depend on input capacitor esr: v out_esr i l esr ? = v out_c i l 1 8c out f sw ?? -------------------------------------- - ? = v out_esr i out esr ? = v out_c l i out 2 ? 2c out v l ?? ------------------------------------- - = d max v in v out ? ? i rms i out d1d ? () ? ? = pesri rms 2 ? =
l6726a 20 a demonstration board doc id 12754 rev 4 23/35 10 20 a demonstration board l6726a demonstration board realizes on a four-layer pcb a step-down dc/dc converter and shows the operation of the device in a general purpose application. input voltage can range from 5 v to 12 v bus. output voltage is programmed to 1.25 v. the voltage regulator can deliver up to 20 a output current. the switching frequency is 270 khz. figure 13. 20 a demonstration board (left) and components placement (right) figure 14. 20 a demonstration board top (left) and bottom (right) layers
20 a demonstration board l6726a 24/35 doc id 12754 rev 4 figure 15. 20 a demonstration board inner layers
l6726a 20 a demonstration board doc id 12754 rev 4 25/35 figure 16. 20 a demonstration board schematic hsd hsd vin_power lsg1 ugate boot boot phase gnd vcc gnd comp fb comp vcc_pin fb out out out out out out out out out out out out out out out out out phase out lsg2 lsg2 lsg2 lsg2 lsg2 lsg2 lsg2 lsg2 lsg2 lsg2 lsg2 lsg2 ugate hsg lgate lgate vcc vcc_pin lgate phase out hsg phase hsd gnd lsg1 phase gnd lsg2 phase 0 0 0 0 0 0 0 vin_power gndin_power 0 vcc gndcc 0 0 0 0 0 0 0 0 0 0 0 vout 0 gndout 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 & r p s h q v d w l r q 1 h w z r u n & r p s d w l e l o l w \ e h w z h h q / $ / / $ ! 5 1 & 5 5 1 & 5 i r u 2 & 6 ( 7 / ! 5 5 1 & 5 i r u 2 & 6 ( 7 5 5 & d o o r z v l p s o h p h q w l q j ' 5 2 2 3 ) x q f w l r q $ g g l w l r q d o 6 2 p r v i h w d q g , q g x f w r u ! i r u i x u w k h u f r p s d w l e l o l w \ " c33 nc c33 nc r14 nc r14 nc comp comp 1 2 l2 t60-18 6ts l2 t60-18 6ts 1 3 2 q6 nc q6 nc fb fb gnd gnd vout1 vout1 c21 nc c21 nc r4 1.8 r4 1.8 ugate ugate c13 4.7uf c13 4.7uf 4 5 1 6 7 8 2 3 q1 nc q1 nc c34 nc c34 nc r13 3.9k r13 3.9k 4 5 1 6 7 8 2 3 q2 nc q2 nc c37 nc c37 nc r8 nc r8 nc c23 6.8nf c23 6.8nf r3 0 r3 0 c36 nc c36 nc r11 0 r11 0 c15 nc c15 nc c22 nc c22 nc c27 nc c27 nc gndout1 gndout1 gndin1 gndin1 1 3 2 q4 std70nh02lt4 q4 std70nh02lt4 c16 nc c16 nc c3 nc c3 nc r9 2.2k r9 2.2k c38 1uf c38 1uf r17 3.3 r17 3.3 c5 nc c5 nc c14 1uf c14 1uf vin1 vin1 c28 nc c28 nc phase phase c19 nc c19 nc c10 100nf c10 100nf c4 nc c4 nc c35 470pf c35 470pf c17 nc c17 nc c11 4.7uf c11 4.7uf r6 nc r6 nc r12 0 r12 0 1 3 2 q5 std95nh02lt4 q5 std95nh02lt4 c7 nc c7 nc c31 nc c31 nc r10 nc r10 nc c29 nc c29 nc c6 nc c6 nc r18 20k r18 20k c18 2200uf c18 2200uf c25 2200uf c25 2200uf r7 2k r7 2k r5 0 r5 0 1 2 l1 nc l1 nc r15 nc r15 nc c2 1800uf c2 1800uf c1 1800uf c1 1800uf r1 3.3 r1 3.3 lgate lgate c9 nc c9 nc c32 nc c32 nc c20 nc c20 nc c24 68nf c24 68nf d1 1n4148 d1 1n4148 c12 4.7uf c12 4.7uf r16 0 r16 0 vcc 5 gnd 3 fb 6 ugate 2 boot 1 comp 7 phase 8 lgate 4 l6726a/27 u1 l6726a/27 u1 4 5 1 6 7 8 2 3 q3 nc q3 nc vcc vcc c30 nc c30 nc c26 nc c26 nc c8 nc c8 nc r2 3.3 r2 3.3
20 a demonstration board l6726a 26/35 doc id 12754 rev 4 table 6. 20 a demonstration board - bill of material qty reference description package capacitors 2c1, c2 electrolytic cap 1800 f 16 v nippon chemi-con kzj or kzg radial 10 x 25 mm 1 c10 mlcc, 100 nf, 25 v, x7r smd0603 3 c11 to c13 mlcc, 4.7 f, 1 6 v, x 5 r murata grm31cr61c475ma01 smd1206 2 c14, c38 mlcc, 1 f, 16 v, x7r smd0805 2c18, c25 electrolytic cap 2200 f 6.3 v nippon chemi-con kzj or kzg radial 10 x 20mm 1 c23 mlcc, 6.8 nf, x7r smd0603 1 c24 mlcc, 68 nf, x7r 1 c35 mlcc, 470 pf, x7r resistors 3 r1, r2, r17 resistor, 3r3, 1/16 w, 1% smd0603 3 r3, r5, r16 resistor, 0r, 1/8 w, 1% smd0805 1 r4 resistor, 1r8, 1/8 w, 1% 2 r11, r12 resistor, 0r, 1/16 w, 1% smd0603 1 r9 resistor, 2k2, 1/16 w, 1% 1 r13 resistor, 3k9, 1/16 w, 1% 1 r7 resistor, 2k, 1/16 w, 1% 1 r18 resistor, 20k, 1/16 w, 1% inductor 1l1 inductor, 1.25 h, t60-18, 6turns easymagnet ap106019006p-1r1m na active components 1 d1 diode, 1n4148 or bat54 sot23 1 q5 std70nh02lt4 dpack 1 q6 std95nh02lt4 1 u1 controller, l6726a so8
l6726a 20 a demonstration board doc id 12754 rev 4 27/35 10.1 board description 10.1.1 power input (vin) this is the input voltage for the power conversion. the high-side mosfet drain is connected to this input. supply must be compliant with vin recommended operating conditions and capacitors rating. if vin voltage is compliant also to vcc range listed in recommended operating conditions, it can supply also the devi ce through r16 resistor. 10.1.2 power output (vout) this is the output voltage of the power conversion. the output voltage is programmed to 1.25 v. it can be changed by replacing r13 (adjusting of compensation network may be needed). r18 allows to adjust ocp threshold. 10.1.3 ic additional supply (vcc) the controller can be supplied separately from the power conversion through vcc input. in this case, to separate vcc from vin, r16 resistor must be removed. 10.1.4 test points the following test points are provided to allow easy probing of important signals: ? comp: output of the error amplifier; ? fb: inverting input of the error amplifier; ? ph: phase pin of the device; ? lg: low-side gate pin of the device; ? ug: high-side gate pin of the device. 10.1.5 demonstration board efficiency figure 17. 20 a demonstration board efficiency 50 55 60 65 70 75 80 85 90 95 100 0 2 4 6 8 10 12 14 16 18 20 22 output current [a] efficiency [%] vin=12v, vout=1.25v vin=5v, vout=1.25v vin=12v, vout=2.5v vin=5v, vout=2.5v
5 a demonstration board l6726a 28/35 doc id 12754 rev 4 11 5 a demonstration board l6726a demonstration board realizes on a two-layer pcb a step-down dc/dc converter and shows the operation of the device in a general-purpose low-current application. input voltage can range from 5 v to 12 v bus. output voltage is programmed at 1.25 v. the application can deliver an output current in excess of 5 a. the switching frequency is 270 khz. figure 18. 5 a demonstration board (left) and components placement (right) figure 19. 5 a demonstration board top (left) and bottom (right) layers
l6726a 5 a demonstration board doc id 12754 rev 4 29/35 figure 20. 5 a demonstration board schematic phase pin boot boot gnd fb comp out out out out out out out out out out out out out out out out ugate hsg1 lgate lgate vcc vcc_pin gnd lgate ugate phase pin comp out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out out lsg1 lsg1 lsg1 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc out out out out out out out out out out vin_power fb fb fb phase hsd 0 0 0 vin_power gndin_power 0 vcc gndcc 0 0 0 vout 0 gndout 0 0 0 0 0 0 0 0 & r p s h q v d w l r q 1 h w z r u n ! s o d f h q h d u w k h f r q w u r o o h u " ( o h f w u r o \ w l f f d s d f l w r u ! g x d o i r r w s u l q w " 7 d q w d o x p f d s d f l w r u v ! g x d o i r r w s u l q w " f h u d p l f f d s d f l w r u v ! g x d o i r r w s u l q w " f h u d p l f f d s d f l w r u v ! s o d f h q h d u + 6 p r v " c12 10uf c12 10uf r1 3.3 r1 3.3 r13 3.9k r13 3.9k r16 0 r16 0 c39 22uf c39 22uf c35 2.2nf c35 2.2nf r14 nc r14 nc 1 2 8 7 u5a sts9d8nh3ll u5a sts9d8nh3ll gnd gnd r5 0 r5 0 phase phase c23 6.8nf c23 6.8nf r4 1.8 r4 1.8 c18 nc c18 nc r10 0 r10 0 c30 330uf c30 330uf vcc vcc c14 1uf c14 1uf r17 3.3 r17 3.3 gndin1 gndin1 c40 nc c40 nc vin1 vin1 c29a nc c29a nc c36 nc c36 nc r3 0 r3 0 d1 bat54 d1 bat54 c38 1uf c38 1uf r8 nc r8 nc 1 2 l2 2.2uh l2 2.2uh boot 1 ugate 2 gnd 3 lgate/oc 4 vcc 5 fb 6 comp 7 phase 8 l6726a u1 l6726a l6726a u1 l6726a r7 820 r7 820 c29 nc c29 nc c10 100nf c10 100nf c51 10uf c51 10uf r18 nc r18 nc 3 4 6 5 u5b sts9d8nh3ll u5b sts9d8nh3ll comp comp ugate ugate fb fb vout1 vout1 r9 2.2k r9 2.2k gndout1 gndout1 c24 220nf c24 220nf 1 2 l3 nc l3 nc r2 3.3 r2 3.3 lgate lgate
5 a demonstration board l6726a 30/35 doc id 12754 rev 4 table 7. 5 a demonstration board - bill of material 11.1 board description 11.1.1 power input (vin) this is the input voltage for the power conversion. the high-side mosfet drain is connected to this input. supply must be compliant with vin recommended operating conditions and capacitors rating. if vin voltage is compliant also to vcc range listed in recommended operating conditions, it can supply also the devi ce through r16 resistor. qty reference description package capacitors 2c12, c51 10 f, 2 5 v, x 5 r murata grm31cr61e106ka12 smd1206 1 c10 mlcc, 100nf, 25v, x7r smd0603 2 c14, c38 mlcc, 1 f, 16 v, x7r smd0805 1c39 mlcc, 22 f, 6.3 v, x5r murata grm31cr60j226me19 smd1206 1c30 330 f, 6.3 v, 40 m sanyo 6tpb330m smd7343 1 c23 mlcc, 6.8 nf, x7r smd0603 1 c24 mlcc, 220 nf, x7r 1 c35 mlcc, 2.2 nf, x7r resistors 1 r4 resistor, 1r8, 1/8 w, 1% smd0805 4 r3, r5, r10, r16 resistor, 0r, 1/16 w, 1% smd0603 3 r1, r2, r17 resistor, 3r3, 1/16 w, 1% 1 r9 resistor, 2k2, 1/16 w, 1% smd0603 1 r13 resistor, 3k9, 1/16 w, 1% 1 r7 resistor, 820r, 1/16 w, 1% inductor 1l1 inductor, 2.20 h, wurth 744324220lf na active components 1 d1 diode, bat54 sot23 1 q5 mosfet, sts9d8nh3ll so8 1 u1 controller, l6726a so8
l6726a 5 a demonstration board doc id 12754 rev 4 31/35 11.1.2 power output (vout) this is the output voltage of the power conversion. the output voltage is programmed to 1.25 v. it can be changed by replacing r13 (adjusting of compensation network may be needed). adding r18 allows to adjust ocp threshold. 11.1.3 ic additional supply (vcc) the controller can be supplied separately from the power conversion through vcc input. in this case, to separate vcc from vin, r16 resistor must be removed. 11.1.4 test points the following test points are provided to allow easy probing of important signals: ? comp: output of the error amplifier; ? fb: inverting input of the error amplifier; ? ph: phase pin of the device; ? lg: low-side gate pin of the device; ? ug: high-side gate pin of the device. 11.1.5 demonstration board efficiency figure 21. 5 a demonstration board efficiency 50 55 60 65 70 75 80 85 90 95 100 0123456 output current [a] efficiency [%] vin = 12v, vout = 1.25v vin = 5v, vout = 1.25v vin = 12v, vout = 2.5v vin = 5v, vout = 2.5v
package mechanical data l6726a 32/35 doc id 12754 rev 4 12 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark.
l6726a package mechanical data doc id 12754 rev 4 33/35 table 8. so-8 mechanical data dim. mm. inch min typ max min typ max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d (1) 1. d and f does not include mold flash or protrusions . mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. 4.80 5.00 0.189 0.197 e 3.80 4.00 0.15 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 k 0 (min.), 8 (max.) ddd 0.10 0.004 figure 22. package dimensions
revision history l6726a 34/35 doc id 12754 rev 4 13 revision history table 9. document revision history date revision changes 16-oct-2006 1 initial release. 26-oct-2006 2 mechanical data dimensions updated 30-jul-2007 3 updated figure 1 on page 4 , tables 2 , 3 , 4 , 5 23-mar-2010 4 added: section 9 on page 21 , section 10 on page 23 , section 11 on page 28 updated: table 5 on page 7
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